By W. Greiner, S. Schramm, E. Stein

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G. clock frequency, input common-mode level or supply voltage. In a simple flash ADC with N bits, 2N − 1 comparators in parallel are necessary. 5 Vref /(2N − 1). In reality no exact value for the sensitivity can be measured, because there is a considerable influence of noise. If at an ideal offset- and hysteresis free comparator the influence of noise is assumed to be not present, the sensitivity is defined by the minimal input voltage difference, at which the comparator in a distinct time (in most cases the half clock period) still has a correct decision, which can be interpreted by following logic gates.

It is assumed, that the comparator has time for a valid decision so that no metastabilty error occurs. The higher the input voltage difference INP−INN, the lower is the chance for a wrong decision. In most cases the noise is assumed to be a stationary random stochastic process, where the probability density function (pdf) of the amplitude of the noise is assumed to be mean free and Gaussian. There are different noise sources, which can be combined to an overall input referred noise source. • The noise of the sources of the signals, which are applied to the input of the comparator disturb the decision.

Santner, T. Hartnig, F. 13μm digital CMOS, Design, Automation and Test in Europe Conference and Exhibition (DATE’05), Vol. 3, pp. 223–226 (2005) 10. H. Dang, M. Sawan, Y. Savaria, A novel approach for implementing ultra-high speed flash ADC using MCML circuits. IEEE Int. Symp. Circuits Syst. 6, 6158–6161 (2005) 11. S. Sheikhaei, S. Mirabbasi, A. 18μm CMOS. IEEE canadian conference on electrical and computer engineering, pp. 698–701 (2005) 12. T. Kobayashi, K. Nogami, T. Shirotori, Y. Fujimoto, A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture.